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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Figure 5. XGXS Transmit Path
PLL
0 °
156MHz
PLL
TCK78B
xgmii_txclk_156
36b
HDOUT[P:N]_BA
xgmii_tx_data[31:0]
XGMII
TX
72b@
156MHz
72b@
36b
36b
HDOUT[P:N]_BB
HDOUT[P:N]_BC
xgmii_tx_ctrlt[3:0]
DDR
Input
SEL
SEL
156MHz
36b
HDOUT[P:N]_BD
78MHz
Packet
Generator
XGMII loopback
(to RX path)
XAUI loopback
(from RX path)
Figure 6. XGXS Transmit Direction Data Translations
xgmii_tx_data[7:0]
xgmii_tx_ctrl[0]
xgmii_tx_data[15:8]
xgmii_tx_ctrl[1]
xgmii_tx_data[23:16]
xgmii_tx_ctrl[2]
xgmii_tx_data[31:24]
xgmii_tx_ctrl[3]
XGMII
XGXS Transmit Function
C 0 1 2 3 4 5 6 7
XGXS mapping
K A B C D E F G H
10b/8b decoding
a b c d e f g h i
j
XAUI Lane 0
Lane 1
Lane 2
Lane 3
XGMII and Slip Buffers
The 10Gigabit Media Independent Interface (XGMII) supported by the XGXS solution conforms to Clause 46 of
IEEE 802.3ae.The XGMII is composed of independent transmit and receive paths. Each direction uses 32 data sig-
nals, four control signals and a clock. The 32 data signals in each direction are organized into four lanes of eight
signals each. Each lane is associated with a control signal as shown in Table 1.
Table 1. XGMII Transmit and Receive Lane Associations 1
Tx Data (xgmii_tx_data)
Tx Control (xgmii_tx_ctrl)
Rx Data (xgmii_rx_data)
[7:0]
[15:8]
[23:16]
[31:24]
Rx Control (xgmii_rx_ctrl)
[0]
[1]
[2]
[3]
XAUI Lane
0
1
2
3
1. The XGMII TX signals are XGXS inputs to the transmit path (XGMII to XAUI). The XGMII RX signals are XGXS outputs of
the receive path (XAUI to XGMII).
6
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